1. Field of the Invention
This invention relates to a semiconductor storage unit, a semiconductor device and a display device as well as to a liquid crystal display and an image receiving apparatus. More specifically, the present invention concerns a semiconductor storage unit that accumulates a charge in an insulating material having a level capable of trapping a charge, a semiconductor device and a display device provided with such a semiconductor storage unit, as well as a liquid crystal display and an image receiving apparatus.
2. Description of the Related Art
Conventionally, a non-volatile memory using a silicon nitride film has been proposed as a non-volatile memory to be formed on an insulating substrate such as a glass substrate. Examples of such a non-volatile memory include a semiconductor non-volatile storage unit disclosed in JP-A No. 11-87545. FIG. 22 shows the semiconductor storage unit disclosed in JP-A No. 11-87545, and in this drawing, reference numeral 901 represents an insulating substrate, 902 is a base insulating film, 911 is a semiconductor layer, 921 is a bottom insulating film, 922 is a charge trap insulating film (silicon nitride), 923 is a top insulating film, and 931 is a control gate. In this structure, a gate insulating film functioning as a memory storage unit has an ONO (Oxide-Nitride-Oxide) structure. A rewriting process of stored information is carried out by injecting a charge from the semiconductor layer 911 to the charge trap insulating film 922. Depending on the quantity of charge accumulated in the charge trap insulating film 922, the threshold value of a memory element serving as a field effect transistor changes. By detecting this change in the threshold value, the reading process of the stored information is carried out.
Moreover, JP-A No. 2000-294662 has disclosed a non-volatile semiconductor memory element in which a gate insulating film and a gate electrode are formed on a semiconductor layer having a channel region, and source and drain regions to construct a transistor so that a charge is injected into the gate insulating film. This memory element is characterized in that an oxide of a gate electrode material is formed on the surface of the gate electrode so that a compression stress is applied to the interface of the gate insulating film.
However, the semiconductor non-volatile storage unit disclosed in JP-A No. 11-87545 is designed so that the gate insulating film has a three-layer structure (ONO structure) in which upper and lower insulating films (the bottom insulating film 921 and the top insulating film 923) sandwich the charge trap insulating film 922, and this structure causes a problem in that the number of processes increases so as to form the gate insulating film. Moreover, the non-volatile semiconductor memory element described in JP-A No. 2000-294662 needs to form an oxide of the gate electrode material on the surface of the gate so as to apply a compression stress to the interface of the gate insulating film.